//接收数据模块
module recv_data   
(
    input                       rst,
    input                       clk_100M,
    input                       clk_400M,
    input                       rx,
    output  reg     [9:0]       rx_data,
    output  reg                 rx_data_en
);

localparam SYNC1 = 10'b1010_1010_10;
localparam SYNC2 = 10'b1010_1010_11;

wire                            rx_bit;
wire                            rx_bit_en;

reg         [3:0]               bit_count;
reg         [9:0]               bit_sft;
reg         [9:0]               sync_shift;

reg                             fr_sync1, fr_sync2;
reg                             fr_sync;
reg                             fr_end;
reg         [7:0]               fr_count;

always @ (posedge clk_400M or posedge rst) begin
    if (rst) begin
        rx_data     <= 0;
        rx_data_en  <= 0;
        bit_count   <= 0;
        bit_sft     <= 0;
        fr_sync1    <= 0;
        fr_sync2    <= 0;
        fr_sync     <= 0;
        fr_end      <= 0;
        fr_count    <= 0;
    end
    else begin
        if (rx_bit_en) begin
            bit_sft     <= {bit_sft[8:0],rx_bit};
            sync_shift  <= {sync_shift[8:0],bit_sft[9]};
        end
        
        if (fr_sync) fr_sync2 <= 1'b0;
        else if (bit_sft == SYNC2) fr_sync2 <= 1'b1;
        
        if (fr_sync) fr_sync1<=1'b0;
        else if (sync_shift==SYNC1) fr_sync1 <= 1'b1;
        
        if (fr_end) fr_sync<=1'b0;
        else if (fr_sync1 & fr_sync2 & rx_bit_en) fr_sync <= 1'b1;
        
        if(fr_sync) begin
            if (rx_bit_en) begin
                if (bit_count == 9) bit_count <= 0;
                else  bit_count <= bit_count + 1;
            end
        end
        
        rx_data_en <= 0;
        
        if (bit_count == 9) begin
            rx_data <= bit_sft;
            rx_data_en <= 1'b1;
        end
        
        fr_end <= 1'b0;

        if (rx_data_en & rx_bit_en)
            if (fr_count == 15) begin
                fr_end <= 1'b1;
                fr_count <= 0;
            end
        else fr_count <= fr_count + 1;
    end
end

recv_bit recv_bit_inst
(
    .rst            (rst),
    .clk_400M       (clk_400M),
    .rx             (rx),
    .rx_bit         (rx_bit),
    .rx_bit_en      (rx_bit_en),
    .rx_r           (),
    .rx_rr          (),
    .nrx_r          (),
    .nnrx_r         (),
    .rx_rg          (),
    .rx_fg          (),
    .rx_dg          ()
);

endmodule 